Manufacturing method of semiconductor device

ABSTRACT

After deposition of a conductor film made of titanium tungsten over a main surface of a semiconductor substrate formed with grooves, a conductor film made of aluminium is further deposited. Subsequently, the conductor film is made to reflow and run into the grooves. Thereafter, while heating, conductor films are respectively deposited, thereby causing the conductor films to run into the grooves. The provision of the conductor film suppresses or prevents aluminium in the conductor films and silicon in the semiconductor substrate from reacting with each other upon reflowing of the conductor films.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a manufacturing technique of a semiconductor device and more particularly, to a technique effective for application to wiring techniques having a step of burying a conductive film made mainly of aluminium (Al) inside an opening for wiring.

[0002] The wiring technique studied by us is, for example, one set out below. Initially, an opening for wiring is formed in a semiconductor substrate, after which a titanium (Ti) film is, for example, deposited on the semiconductor substrate including the inside of the wiring opening. Subsequently, an aluminium film is, for example, deposited on the titanium film at low temperatures and high power in a relatively large thickness (e.g. about 200 nm). Thereafter, the semiconductor substrate is maintained at high temperatures (e.g. about 400° C.) until the aluminium film is deposited to a desired thickness (e.g. about several hundreds of nanometers). The high temperatures are kept continued over several minutes to reflow the aluminium film, thereby causing the opening to be buried therewith.

[0003] It will be noted that a wiring technique is set out, for example, in Japanese Laid-open Patent Application No. 2001-267569. In this application, a technique is disclosed wherein a source electrode of power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is constituted of a barrier layer made, for example, of titanium tungsten, titanium nitride (TiN) or the like, built up with pure aluminium thereon so as to prevent failure from occurring upon ultrasonic wire bonding.

SUMMARY OF THE INVENTION

[0004] We have found that the wiring technique studied by us has the following problems. If the amount of buried aluminium inside the opening for wiring has increased, then it becomes necessary to heat the aluminium to higher temperatures so as to enhance the reflowability of aluminium. Nevertheless, the barrier properties of titanium is not satisfactory, so that when heating temperatures exceeds, for example, about 400° C., the reaction between aluminium and silicon (Si) proceeds, with some possibility of causing junction leakage failure.

[0005] An object of the invention is to provide a technique capable of improving the reliability of semiconductor devices.

[0006] The above and other objects and novel features of the invention will become apparent from the following description with reference to the accompanying drawings.

[0007] A typical embodiment of the invention among those embodiments disclosed in this application is briefly described below.

[0008] According to the invention, there is provided a manufacturing method of a semiconductor device, which comprises the steps depositing, on a semiconductor substrate including an opening for wiring, a first conductive film having such a structure capable of suppressing or preventing the reaction between aluminium atom and constituent atom of the semiconductor substrate upon thermal treatment for re-melting a conductive film made mainly of aluminium, and thermally treating a conductor film made mainly of aluminium after or in the course of deposition thereof until re-melting thereby causing the aluminium-based conductor film to flow and run into the opening for wiring.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a sectional view of an essential part in the course of the manufacture of a semiconductor device according to one embodiment of the invention;

[0010]FIG. 2 is a sectional view of the essential part in the course of manufacture of the semiconductor device subsequent to FIG. 1;

[0011]FIG. 3 is a sectional view of the essential part in the course of manufacture of the semiconductor device subsequent to FIG. 2;

[0012]FIG. 4 is a sectional view of the essential part in the course of manufacture of the semiconductor device subsequent to FIG. 3;

[0013]FIG. 5 is an enlarged, sectional view of the essential part of FIG. 4;

[0014]FIG. 6 is a flowchart for burying a groove formed in the manufacturing step of the semiconductor device of FIG. 4;

[0015]FIG. 7 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 4;

[0016]FIG. 8 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 7;

[0017]FIG. 9 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 8;

[0018]FIG. 10 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 9;

[0019]FIG. 11 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 10;

[0020]FIG. 12 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 11;

[0021]FIG. 13 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 12;

[0022]FIG. 14 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 13;

[0023]FIG. 15 is a sectional view of an essential part in the course of the manufacture of a semiconductor device according to another embodiment of the invention;

[0024]FIG. 16 is a section, taken along the line X1-X1 of FIG. 15;

[0025]FIG. 17 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 16;

[0026]FIG. 18 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 17;

[0027]FIG. 19 is a plan view of an essential part in the course of the manufacture of a semiconductor device according to a further embodiment of the invention;

[0028]FIG. 20 is a section, taken along the line X2-X2 of FIG. 19;

[0029]FIG. 21 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 20;

[0030]FIG. 22 is an enlarged, sectional view of the essential part in the course of the manufacture of the semiconductor device subsequent to FIG. 21; and

[0031]FIG. 23 is a sectional view of an essential part in the course of manufacture of a semiconductor device according to a still further embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Although embodiments of the invention are illustrated by division into a plurality of sections or sub-embodiments if expediently necessary, these are not mutually irrelevant to one another unless otherwise stated. More particularly, one may be in relation with a modification, details, supplemental explanation and the like of part or all of others. In the following embodiments, where reference is made to the number and other parameters of elements (including the number, numerical value, quantity, range and the like), they should not be construed as limiting to specified values or numbers, respectively, except the case where otherwise specified or where limited to a specific value apparently in principle. That is, those values smaller than or larger than the respective specified values may also be within the scope of the invention. Moreover, it is as a matter of course that constituent elements (including steps) in the following embodiments are not always essential except the case where otherwise specified or where such elements are considered to be apparently essential in principle. Likewise, if reference is made to the shape, position, relation and the like of the constituent elements, then substantially like or similar shapes and the like are also within the scope of the invention except the case where otherwise specified or where such shapes should not be apparently included in principle. This is true of the above-indicated numbers and ranges. Throughout the drawings for illustrating the embodiments of the invention, like reference numerals indicate like parts or members having the same function, which are not repeatedly explained after once having been illustrated. In the embodiments of the invention, with the expression, for example, of “composed or made of aluminium”, it is intended to use aluminium as a main component. In general, it is assumed that highly pure aluminium contains impurities and thus, a member made, for example, of aluminium should not be construed as excluding the inclusion of additives or impurities therein. This is not limited to aluminium, but is applied to other types of metals and the like (such as titanium tungsten, tungsten, tantalum, nitrides thereof, and tungsten silicide or its nitride).

[0033] The embodiments of the invention are described in detail with reference to the accompanying drawings.

[0034] (Embodiment 1)

[0035] A semiconductor substrate of Embodiment 1 is one that has, for example, n-channel power MISFET (Power Metal Insulator Semiconductor Field Effect Transistor: power transistor) having a trench gate structure. An example of a manufacturing method of a semiconductor device according to Embodiment 1 of the invention is described with reference to FIGS. 1 to 14.

[0036]FIG. 1 shows a sectional view of an essential part during the manufacture of a semiconductor device of Embodiment 1. A semiconductor device (hereinafter referred to simply as substrate) is a so-called epitaxial wafer (hereinafter referred to simply as wafer) having, for example, such a structure that an n⁻ type semiconductor layer 1 b is deposited on an n⁺ semiconductor layer 1 a by an epitaxial technique. The semiconductor layers 1 a, 1 b are made, for example, of single crystal silicon (Si), respectively. The impurity concentration in the semiconductor layer 1 a is, for example, at about 2.0×10¹⁹ cm⁻³, and that of the semiconductor layer 1 b is, for example, at about 1.0×10¹⁶ cm⁻³. The semiconductor layer 1 b is formed with a p⁻ type semiconductor region 2 (well: first semiconductor region) therein. This semiconductor region 2 is one where channels for a plurality of power MISFET's (hereinafter referred to simply as power MIS('s) are formed. The semiconductor region 2 is formed, for example, by distributing boron (B) from the main surface of the semiconductor layer 1 b to an intermediate position along the thickness of the semiconductor layer 1 b. The peak concentration of the impurity in the semiconductor region 2 is set, for example, at about 1×10¹⁶ to about 1×10¹⁸ cm⁻³. A p-type semiconductor region (well) 3 is formed along the outer peripheral end of the semiconductor region 2 in the semiconductor layer 1 b. Boron is, for example, contained in this semiconductor region 3. An isolation region 4 made, for example, of silicon oxide (SiO₂ or the like) is formed, according to a LOCOS (Local Oxidization of Silicon) technique or the like, at the isolation region in the main surface of the semiconductor layer 1 b. The isolation region 4 may be in the form of a groove (trench isolation). The active region surrounded by the isolation region 4 becomes a power MID-forming region. This active region is formed with a plurality of grooves (first grooves) 5 therein. The grooves 5 are, respectively, provided for every cell, and extend from the main surface of the semiconductor layer 1 b to an intermediate position along the depth of the semiconductor layer 1 b as viewed in section and extend along a certain direction as viewed in plane. The inner wall surfaces of the groove 5 and the upper surface of the semiconductor layer 1 b at an area around the opening of the groove 5 are formed thereon with a gate insulating film 6 made, for example, of a silicon oxide film. A trench-type gate electrode 7 of the power MIS is formed on the gate insulating film 6. The gate electrode 7 is made, for example, of a low resistance polysilicon film and is shaped in the form of T in section. More particularly, the gate electrode 7 has a first portion 7 a that is buried inside the groove through the gate insulating film 6 and a second portion 7 b that joins to the first portion 7 a, projects outwardly from the groove and has a width greater than the width of the groove 5 (i.e. a width along a minor direction). At the outer periphery of the power MID-forming region, an extrinsic gate wiring 7L is formed on the main surface of the semiconductor layer 1 b through the gate insulating film 6 and the isolation region 4. The extrinsic gate wiring 7L is integrally formed with the respectively gate electrodes 7 and electrically connected therewith. A cap insulating film (first insulating film) 8 made, for example, of a silicon oxide film is deposited, after pattering, over the gate electrodes 7 and the extrinsic gate wiring 7L. An n-type semiconductor region (second semiconductor region) 9 a serving as a source is formed at a portion of the semiconductor layer 1 b established between adjacent gate electrodes 7. This semiconductor region 9 a is formed by distributing, for example, arsenic (As) from the main surface of the semiconductor layer 1 b to an intermediate position along the depth of the semiconductor region 2, and has been already formed prior to the formation of the groove 5. The peak concentration of the impurity in the semiconductor region 9 a is, for example, at about 1×10¹⁸ to about 1×10²⁰ cm⁻³.

[0037] Next, FIGS. 2 and 3 are, respectively, a sectional view of the essential part during the manufacture of the semiconductor device subsequent to FIG. 1. As shown in FIG. 2, a resist pattern covering regions other than the source region is formed over the main surface of the substrate 1 of FIG. 1, after which arsenic is, for example, ion implanted into the main surface of the substrate 1 through the mask of the resist pattern to form an n-type semiconductor region (second semiconductor region) 9 for source on the surface layer of the semiconductor layer 1 b between adjacent gate electrodes 7. Subsequently, an insulating film 10 made, for example, of a silicon oxide film or the like is deposited over the main surface of the semiconductor layer 1 b of the substrate (wafer) 1 by a CVD (Chemical Vapor Deposition) method, followed by formation of a photoresist pattern (hereinafter referred to as resist pattern) thereon so that the outer peripheral region of the power MIS-forming region is covered therewith but others are exposed. In this condition, the insulating film 10 on the substrate 1 is etched back according to an anisotropic dry etching technique to form the respective electrodes 7 at the power MIS-forming region and side walls (second insulating films) 10 a at the side surfaces of the cap insulating films 8 along with an insulating film 10 b being formed around the power MIS-forming region. Subsequently, as shown in FIG. 3, the cap insulating films 8, side walls 10 a and insulating film 10 b are used as an etching mask to etch the exposed portions of the semiconductor layer 1 b by a dry etching technique to form grooves (second grooves) 11. The respective grooves extend from the main surface of the semiconductor layer 1 b to an intermediate position along the depth of the semiconductor region 2 as viewed in section and also extend along a given direction as viewed in plane. Thereafter, boron difluoride (BF₂) is, for example, ion implanted into the semiconductor layer 1 b at 80 keV and about 3×10¹⁵ cm⁻², thereby forming a p⁺-type semiconductor region (third semiconductor region) 12 at the bottom of the groove 11.

[0038] Next, FIG. 4 is a sectional view of the essential part during the manufacture of the semiconductor device subsequent to FIG. 3. FIG. 5 is an enlarged, sectional view of region A in FIG. 4. In this step, the substrate 1 is subjected to wet etching to slightly etch the exposed surface portions of the insulating film 10 and the gate insulating film 6 in such a way that the side surface of the side wall 10 a is kept away from the side surface of the groove 11. In this way, part of the main surface of the semiconductor layer 1 b around the opening of the groove 11 is exposed. This contributes to increasing the contact area between the source electrode and the semiconductor source region 9 a. The above-mentioned etching permits a groove (second groove) 13 to be formed, which groove is located over and is wider than the groove 11 and runs into the groove 11. As shown in FIG. 5, the total depth D1 of the grooves 11, 13 is, for example, at about 1.2 μm, and the depth D2 of the groove 11 is, for example, at 0.4 μm. The depth D3 of the groove 13 is, for example, at about 0.8 μm and the width D4 of the groove 11 is, for example, at about 0.5 to 0.6 μm. In this connection, however, the wiring formation method of Embodiment 1 described hereinafter may also be applied to the case where no etching is carried out for the purpose of the formation of the groove 13, i.e. the case of a structure wherein the groove 13 is so arranged that its width is not larger than but equal to that of the groove 11. After completion of the etching, ordinary photolithographic and dry etching techniques using a resist pattern as a mask are performed to form a contact hole 14 so that part of the extrinsic gate wiring 7L is exposed at the insulating film 10 b and the cap insulating film 8.

[0039] Such grooves 11, 13 as formed in the power MIS are, respectively, larger in width than a contact hole or a through-hole of a semiconductor device having an ordinary logic circuit or memory circuit, with the tendency that the aspect ratio increases owing to the reduction in size between adjacent cells accompanied by the requirement for improving the degree of integration of the cells of power MIS. In order to bury such relatively great, deep grooves 11, 13 with an aluminium (Al) film, it is desirable to raise the reflow temperature after or during deposition of the aluminium film. Nevertheless, if the reflow temperature increases and particularly, exceeds 400° C., the reaction between aluminium used as a wiring material and silicon in the substrate 1 proceeds, with the attendant problem that junction failure takes place at the channel portion of power MIS. On the other hand, a problem is involved as to how the grooves 11, 13 are, respectively, buried in a space-free, continuous condition so as to lower the ON resistance (i.e. ON resistance between the source electrode and the drain electrode) of power MIS. To cope with the problem, the following procedure is performed according to Embodiment 1.

[0040]FIG. 6 is a flow chart for burying the grooves 11, 13. FIGS. 7 to 13 are, respectively, an enlarged, sectional view showing a portion corresponding to the region A of FIG. 4 in the course of the manufacture of the semiconductor device along the line of the flow chart of FIG. 6. As shown in FIG. 7, a conductor film (first conductor film) 15 a is deposited on the main surface of the substrate (wafer) 1 (step 100 in FIG. 6). This permits the thin conductor film 15 a to be deposited on the inner surfaces (inner wall surfaces and bottom surface) of the grooves 11, 13 and the contact hole 14 (see FIG. 4) so that the grooves 11, 13 and the contact hole 14 are not buried completely. This conductor film 15 a has the barrier function of suppressing or preventing the aluminium used as a main wiring material as will be described hereinafter from diffusion into the aluminium film side and also the silicon of the semiconductor layer 1 b from diffusion into the side of the aluminium film used as the main wiring material. Especially, in Embodiment 1, if the reflowing of aluminium described hereinafter is carried out at high temperatures, for example, of 400° C. or over, the conductor film 15 a is considered to provide a structure (from the aspects of material, thickness, function and the like) capable of suppressing or preventing the reaction between aluminium used as a main wiring material and silicon in the semiconductor layer 1 b. According to our studies, it has been found that where titanium (Ti) is selected as a material for the conductor film 15 a, the resultant titanium film is converted to a silicide thereof substantially entirely along the thickness thereof when subjected to annealing after deposition thereof. Eventually, when aluminium used as a main wiring material is deposited and subjected to reflow treatment at high temperatures (of 400° C. or over), the reaction between the aluminium and the silicon proceeds, thus leading to the junction leakage failure at the channel portion of power MIS. In order to suppress or prevent the reaction between aluminium and silicon as mentioned above, the conductor film 15 a should be made of a high heat resistance material, which is not converted into silicide entirely along the thickness of the conductor film 15 a by annealing subsequent to the deposition of the conductor film 15 a. In other words, the conductor film 15 a is so selected as to provide a structure wherein the silicide layer is formed only at a contact portion with the semiconductor layer 1 b and thus, the conductor film 15 a is interposed between the silicide layer and the aluminium film used as a main wiring material in order not to permit direct contact between the silicide layer and the aluminium used as a main wiring material. In this manner, if the thermal treatment temperature of aluminium used as a main wiring material as will be described hereinafter is made high, the reaction between the aluminium and the silicon in the substrate 1 can be suppressed or prevented by means of the conductor film 15 a. Accordingly, the main wiring material of aluminium can be thermally treated at high temperatures and thus, the grooves 11, 13 can be buried with aluminum in an efficiently improved manner. As a specific material for the conductor film 15 a, a number of materials could be selected by us, of which titanium tungsten (TiW) is most preferred. Titanium tungsten has favorable properties that it exhibits low reactivity with silicon, is thermally stable and low in heat resistance, and is low in contact resistance and electric resistance because this material is a kind of metal. Where titanium tungsten is selected as a material for the conductor film 15 a, its thickness is, for example, at about 200 nm. It will be noted that the thickness of the conductor film 15 a means a design thickness (which is substantially equal to a thickness of the conductor film 15 a deposited on the upper surface of the cap insulating film 8 and the insulating film 10 b) The thickness of the conductor film 15 a attached on the side walls and the bottom surfaces of the grooves 11, 13 becomes smaller than the design thickness (of about 200 nm) (the term “design thickness” used hereinafter has the same meaning as set out above).

[0041] Other types of materials for the conductor film 15 a include, for example, high-melting metals such as tungsten (W), tantalum (Ta) and the like. In this case, they are high in heat resistance and are low in contact and electric resistances because of the nature of metal thereof. Further types of materials for the conductor films 15 a include, for example, high melting metal nitride films such as a titanium tungsten nitride film (TiWN), a tungsten nitride film (WN), a tantalum nitride film (TaN) and the like. Still further types of materials for the conductor film 15 a include, for example, tungsten silicide (WSi₂) and nitride thereof (WSiN). Where tungsten silicide (WSi₂) or its nitride (WSiN) is selected, silicon is present in the conductor film 15 a. The bonding between tungsten and silicon is stronger than the bonding between aluminium and silicon, so that the reactivity between aluminium and silicon becomes low. As a result, substantially similar effects are obtained as in the case where titanium tungsten is selected. Using such materials as indicated above or other types of materials as the conductor film 15 a, proper control in thickness of the conductor film 15 a may cause such action and effect as set out hereinabove.

[0042] Next, the substrate (wafer) 1 is annealed in an atmosphere of an inert gas such as, for example, nitrogen gas (N₂) or the like at 650° C. for about 30 minutes (step 101 in FIG. 6). This permits, as shown in FIG. 8, a very thin silicide layer (compound layer) 15 b made, for example, of titanium silicide (TiSi₂) or the like to be formed at the interface of contact of the conductor film 15 a with the semiconductor layer 1 b and the extrinsic gate wiring 7L (see FIG. 4). In Embodiment 1, the conductor film 15 a is not wholly converted to silicide as mentioned above, but the silicide layer 15 b is formed only at the interface portion of contact between the conductor film 15 a and the semiconductor layer 1 b, with the conductor layer 15 b being left at the upper layer or portion thereof. The contact resistance between the source electrode the semiconductor region for source described hereinafter can be reduced through the formation of such a silicide layer 15 b, thus enabling the ON resistance of power MID to be reduced. This treatment can be likewise carried out for the case where the conductor film 15 a is made of a material other than titanium tungsten. In the case, a silicide layer is formed only at a contact portion between the conductor film 15 a and the semiconductor layer 1 b, like the case using titanium tungsten, with the conductor film 15 a being left at an upper layer relative to the silicide layer. Subsequently, as shown in FIG. 9, a conductor film (second conductor film) 15 c made of a high-melting metal film such as of titanium (Ti) or the like is deposited, for example, in a design thickness of about 50 nm by a sputtering method (see step 102 in FIG. 6). In doing so, the conductor film 15 c is so attached as to cover the surface of the conductor film 15 a at the inner surface (including the inner wall surfaces and bottom surfaces) of the grooves 11, 13 and the contact hole 14 without fully burying the grooves 11, 13 and the contact hole 14 (see FIG. 4) therewith. This conductor film 15 c has the functions of improving the wettability of an aluminium film to be subsequently deposited and suppressing or preventing aluminium and silicon from being reacted with each other. The conductor film 15 having the above-stated conductor films 15 a, 15 b, 15 c is an auxiliary wiring material for forming the gate electrode and the source electrode of power MIS.

[0043] Next, as shown in FIG. 10, a conductor film made, for example, of aluminium (a aluminium-based conductor film made mainly of aluminium or a first aluminium-based conductor film made mainly of aluminium) 16 a is deposited on the main surface of the substrate (wafer) 1 by a sputtering method (step 103 in FIG. 6). This conductor film 16 a serves as an underlying film having the function of ensuring the continuity of an aluminium film in a subsequent deposition procedure of hot aluminium and is formed as a film at a low temperature (e.g. a normal temperature: 30° C.). More particularly, when an aluminium film is deposited, under high temperature conditions, on the conductor film 15 c made of titanium or the like, small lumps of aluminium are formed on the surface of the conductor film 15 c, thus not ensuring the continuity of the aluminium film. In order to establish the continuity of an aluminium film, a conductor film 16 a made of an aluminium film is formed under low temperature conditions prior to the formation of an aluminium film under high temperature conditions. The thickness of the conductor film 16 a is at a level sufficient to bury the groove 11 of a relatively small width and particularly, at such a level that the portion of the conductor film 15 c is not exposed at the corner (i.e. a portion formed at the intersection between the main surface of the semiconductor layer 1 b and the side surface of the groove 11) of the semiconductor layer 1 b around the opening of the groove 11. This is for the reason that if part of the conductor film 15 c is exposed, the continuity of a subsequently deposited aluminium film cannot be ensured. The design thickness of the conductor film 16 a formed in this way is, for example, at about 400 nm. At this stage, the conductor film 16 a is in such a state as to be attached through the thin conductor films 15 a, 15 b, 15 c on the inner surfaces (i.e. the inner wall surfaces and bottom surfaces) of the grooves 11, 13 and the contact hole 14 without completely burying the groove 13 and the contact hole 14 (FIG. 4) therewith. After the deposition of the conductor film 16 a, the substrate (water) 1 is annealed, as shown in FIG. 11, within the sputtering apparatus wherein the conductor film 16 a has been deposited, thereby causing the conductor film 16 a to be made to reflow (see step 104 in FIG. 6). In this manner, the conductor film 16 a is made to flow and run into the grooves 11, 13. At this stage, the annealing temperature is set at a temperature, for example, of higher than about 400° C. in Embodiment 1. More particularly, annealing is carried out, for example, at 450° C. for several minutes. This enables the reflow property of aluminium to be improved. More particularly, a great quantity of aluminium is charged or run into the grooves 11, 13 which are fine and has a high aspect ratio, thereby burying the grooves 11, 13 satisfactorily. This permits the electric resistance within the grooves 11, 13 to be reduced and thus, the ON resistance of power MID can be reduced, making it possible to improve the performance of power MIS. As stated hereinabove, in Embodiment 1, the conductor 15 a is formed, so that even if the annealing temperature is set at a level, for example, of higher than 400° C., the reaction between aluminium and silicon in the semiconductor layer 1 b can be suppressed or prevented. Thus, the occurrence of junction failure at the channel portion of power MIS ascribed to the reaction can be suppressed or prevented, with the possibility of leading to improved yield and reliability of power MIS. At this stage, the conductor film 16 a does not completely bury the grooves 11, 13 and the contact hole 14 (see FIG. 4) therewith, but is in a state of being attached to the inner surfaces (i.e. the inner wall surfaces and bottom surfaces) of the grooves 11, 13 and the contact hole 14 through the thin conductor films 15 a, 15 b, 15 c. A recess is left at the upper surface of the conductor film 16 a within the groove 13. Thereafter, a conductor film (second aluminium-based conductor film) 16 b made, for example, of aluminium or the like is deposited, as shown in FIG. 12, by a sputtering method at a low rate within the same sputtering apparatus as used for the deposition of the conductor film 16 a (step 105 in FIG. 6). At the time, the conductor 16 b is deposited while heating the substrate (wafer) 1 from the back side thereof (so-called heat sputtering). In this way, the conductor films 16 a, 16 b flow and run into the grooves 11, 13. The heating temperature is set, for example, at a level of higher than 400° C. and more particularly, at as high as about 450° C. Eventually, a similar effect as in the case of the conductor film 16 a can be obtained. The deposition rate of the conductor film 16 b should be lower than the deposition rate of an aluminium film to be subsequently deposited. This is because the recessed portion in the groove 13 is well buried with the conductor film 16 b while ensuring the continuity of the conductor film 16 b. The deposition rate of the conductor film 16 b is, for example, at 0.4 μm per unit time (of about several minutes). The design thickness of the conductor film 16 b deposited at this stage is about half of the width D3 (see FIG. 5) of the groove 13 and is particularly, for example, at about 400 nm. This permits the remaining recess in the groove 13 to be substantially completely buried with the conductor film 16 b. It will be noted that although a boundary line between the conductor films 16 a, 16 b is indicated by broken line in FIG. 12 only for the sake of ease in viewing the drawing, such a boundary line is not actually formed. Thereafter, a conductor film (second aluminium-based conductor film) 16 c made, for example, of aluminium or the like is deposited on the main surface of the semiconductor substrate (wafer) 1 at a high rate according to a sputtering method within the same sputtering apparatus as used for the deposition of the conductor film 16 b (step 106 in FIG. 6). In this case, the conductor film 16 c is deposited while heating the substrate (wafer) 1 from the back side thereof. The heating temperature is set, for example, at a level of higher than 400° C. and is particularly, for example, at about 450° C. In this way, similar effects as in the case of the conductor films 16 a, 16 b can be obtained. The deposition rate of the conductor film 16 c is made higher than the deposition rate of the conductor film 16 b. This is for the reason that at this stage, the groove 13 is substantially completely buried with the conductor film 16 b, so that priority is put on the shortage in deposition time of the aluminium film over the burying property and continuity of the groove being ensured, thereby improving the throughput. The deposition rate of the conductor film 16 c is, for example, at about 4.1 μm per unit time (of about several minutes, which is the same as the unit time for the deposition rate of the conductor film 16 b). The thickness of the conductor fun 16 c deposited in this time should be one which is sufficient to lower the ON resistance of power MIS and is particularly as thick as about 4.1 μm, for example. The conductor film having the thus deposited conductor films 16 a, 16 b, 16 c, each made mainly of aluminium, is used as the afore-mentioned main wiring material for forming gate and source electrodes. At this stage, the grooves 11, 13 and the contact hole 14 (see FIG. 4) are, respectively, buried with the conductor film 16 to a full extent. According to this Embodiment 1, the aluminium-based conductor film 16 made mainly of aluminium can be buried in the grooves 11, 13, which are greater in size than grooves or holes formed in ordinary semiconductor devices and thus, have a high aspect ratio, in a space-free condition and can also be deposited as thick in the state of ensuring continuity. This enables the ON resistance of power MID to be lowered, thus permitting a great current to pass without exceeding a maximum power loss (drain loss) at a specified reference point temperature. Thus, the performance and reliability of the semiconductor device can be improved. If the grooves 11, 13 are microfabricated, such grooves 11, 13 can be well buried with the conductor film 16. Thus, the microfabrication of the grooves 11, 13 ca be promoted and thus, the degree of integration of cells of power MIS can be improved. Accordingly, the number of cells formed in power MIS per unit area can be increased, thus leading to an improved capacity of semiconductor device. It will be noted that although boundary lines of the conductor films 16 a, 16 b, 16 c are, respectively, indicated by a broken line in FIG. 13 only for the sake of ease in viewing the drawing, these boundary lines are not formed actually.

[0044] Next, FIG. 14 is a sectional view of an essential part in the manufacture of the semiconductor device subsequent to FIG. 13. In this step, the conductor films 16, 15 are, respectively, patterned by ordinary photolithographic and dry etching techniques to form a gate electrode 17 and a source electrode 18, each having the conductor films 16, 15, on the main surface of the substrate 1. The gate electrode 17 is electrically connected to the extrinsic gate wiring 7L via the contact hole 14, and the source electrode is electrically connected to the semiconductor regions 2, 9, 12 of the semiconductor layer 1 b via the grooves 13, 11. After deposition of a surface protective film on the main surface of the substrate 1, a bonding area thereof is removed by etching to form a bonding pad. Thereafter, the substrate (wafer) 1 is polished on the back surface thereof, and a drain electrode is formed at the back surface. Subsequently, a semiconductor device having power MIS is manufactured through an ordinary assembling procedure of semiconductor device. This power MIS is so arranged that in a state where a positive voltage is applied to the drain electrode and a ground voltage (0 V) is applied to the source electrode 18, the power MIS commences to work when a positive voltage is applied to the gate electrode 17 from a state where the gate electrode 17 has been applied with the ground voltage and thus, does not work. When a positive voltage is applied to the gate electrode 17, an inversion layer (n-channel) is formed in the p⁻-type semiconductor region 2, under which the n-type semiconductor region 9 for source and the semiconductor layers 1 a and 1 b for drain are connected through the inversion layer. As a result, electrons pass from the source electrode 18 to the drain electrode at the back surface of the substrate 1 via the n-type semiconductor region 9, inversion layer, semiconductor layer 1 b and semiconductor layer 1 a on the main surface of the substrate 1. More particularly, an electric current passes from the drain electrode to the source electrode 18, so that power MIS is turned on. In this way, the drain current of power MID runs along the thickness of the substrate. On the other hand, when the gate voltage is changed from a positive voltage to a ground or negative voltage, the above-mentioned inversion layer disappears, so that no electric current passes between the n-type semiconductor region 9 and the semiconductor layers 1 a, 1 b, rendering power MIS off.

[0045] (Embodiment 2)

[0046] In Embodiment 2, an application to a Damascene wiring formation technique is illustrated with reference to FIGS. 15 to 18. FIG. 15 is a plan view of an essential part in the manufacture of a semiconductor device of Embodiment 2, and FIG. 16 is a section taken along the line X1-X1 in FIG. 15. FIGS. 17 and 18 are, respectively, a sectional view of the device at a portion corresponding to the line X1-X1 of FIG. 15 in the course of the manufacture of the semiconductor device subsequent to FIG. 16.

[0047] As shown in FIGS. 15 and 16, MISFET (hereinafter referred to simply as MIS) Q is formed, for example, at an active region surrounded with an isolation portion 4 on the main surface of a substrate (wafer) 1. The substrate 1 is not made of an epitaxial wafer, but is made of an ordinary semiconductor wafer. The isolation portion 4 has a so-called trench isolation structure wherein it is formed by burying an insulating film in a groove made in the main surface of the substrate 1. MIS Q has source and drain semiconductor regions 20 formed in the main surface of the substrate 1, a gate insulating film 21 formed on the main surface of the substrate 1, and a gate electrode 22 formed thereon. The semiconductor region 20 is formed by introducing, for example, arsenic (As) or phosphorus (P) if MIS Q is an n-channel and is formed by introducing, for example, boron (B) or boron difluoride (BF₂) for MIS Q being a p-channel. The gate insulating film 21 is made, for example, of a silicon oxide film, a silicon oxynitride film or a builtup structure of a silicon oxide film and a silicon nitride film. The gate electrode 22 is made, for example, of a single film structure of a polysilicon film of low resistance, a so-called polycide structure wherein a silicide film is formed on a low resistance polysilicon film, or a so-called polymetal structure wherein a metal film is provided on a low resistance polysilicon film through a barrier conductor film. The substrate 1 is deposited, on the main surface thereof, with an insulating film made, for example, of a silicon oxide film so as to cover MIS Q therewith. This insulating film 23 is formed with a wiring groove (opening for wiring) 23 a and a contact hole (opening for wiring) 24 b reaching the main surface of the substrate 1 from the bottom. As viewed in plane as shown in FIG. 15, the wiring groove 24 a is formed as a band-shaped pattern extending in vertical directions of FIG. 15. On the other hand, as viewed in section as shown in FIG. 16, the groove 24 a is formed as a rectangular groove having a depth extending to an intermediate position along the thickness of the insulating film 23. The contact hole 24 b, as viewed in plane as shown in FIG. 15, is formed as a circular pattern whose diameter is smaller than the width (minor size) of the wiring groove 24 a, and part (part of the semiconductor regions 20 for source and drain) of the main surface of the substrate 1 is exposed from the bottom of the contact hole 24 b. As viewed in section as shown in FIG. 16, the contact hole 24 b is formed in such a state as to extend from the bottom surface of the wiring groove 24 a to the main surface of the substrate 1.

[0048] As shown in FIG. 17, a conductor film 15 and a conductor film 16 are successively deposited in order from lower layer on the main surface of the substrate 1 in the same manner as in the foregoing Embodiment 1. The conductor films 15, 16 are arranged in the same manner as in Embodiment 1. In Embodiment 2, the conductor film 16 can be well buried in the wiring groove 24 a and the contact hole 24 b in a space-free condition, like Embodiment 1, and deposited while ensuring the continuity thereof. Subsequently, additional conductor films 16, 15 are, respectively, polished by a chemical mechanical polishing (CMP) method, thereby forming a buried wiring 25 having the conductor films 15, 16 within the wiring groove 24 a and the contact hole 24 b.

[0049] (Embodiment 3)

[0050] In Embodiment 3, an application to a buried electrode (plug) formation technique is illustrated with reference to FIGS. 19 to 22. FIG. 19 is a plan view of an essential part in the course of the manufacture of a semiconductor device of Embodiment 3, and FIG. 20 is a sectional view taken along the line X2-X2 of FIG. 19. FIGS. 21 and 22 are, respectively, a sectional view of the device at a portion corresponding to the line X2-X2 of FIG. 19 in the course of the manufacture of the semiconductor device subsequent to FIG. 19.

[0051] As shown in FIGS. 19 and 20, an insulating film 26 made, for example, of a silicon oxide film or the like is deposited on the main surface of a substrate (wafer) 1. This insulating film 26 is formed therein with a contact hole (opening for wiring) 24 b of a circular form in plane that reaches the main surface of the substrate 1. As shown in FIG. 21, conductor films 15, 16 are successively deposited in order from lower layer on the main surface of the substrate 1, like the foregoing Embodiments 1, 2. The conductor films 15, 16 are arranged in the same manner as in Embodiments 1, 2. Accordingly, in Embodiment 3, the conductor film 16 can be well buried in the contact hole 24 b in a space-free condition and deposited while ensuring the continuity thereof, like Embodiments 1, 2. Subsequently, additional conductor films 16, 15 are, respectively, polished according to a CMP method or the like to form a buried electrode (plug) 27 having the conductor films 15, 16 inside the contact hole 24 b as shown in FIG. 22.

[0052] (Embodiment 4)

[0053] In Embodiment 4, a modification of the foregoing Embodiment 3 is described. FIG. 23 is a sectional view of an essential part in the course of the manufacture of a semiconductor device of Embodiment 4. Initially, after carrying out the steps of FIGS. 19 to 21 with respect to the foregoing Embodiment 3, the conductor films 15, 16 of FIG. 21 are, respectively, patterned through a resist pattern as an etching mask according to ordinary photolithographic and dry etching techniques to form wirings 28 having the conductor films 15, 16 on the insulating film 26 as shown in FIG. 23. The wirings 28 are electrically connected to the semiconductor regions 20 for source and drain of MIS Q through the contact holes 24 b, respectively.

[0054] Although the embodiments of the invention which have been made by us have been particularly described hereinabove, the invention should not be construed as limiting to these embodiments and many modifications and changes may be possible without departing from the spirit of the invention.

[0055] For instance, although an application to n-channel power MID has been illustrated in the foregoing Embodiment 1, the invention is not limited to this case, but may be applied to p-channel power MIS.

[0056] Further, an application to power MIS having a trench gate electrode structure has been illustrated in Embodiment 1, and the invention is not limited to this application but may be applied to power MID having a transverse gate electrode structure formed on the main surface of the substrate.

[0057] Moreover, the annealing step 104 in FIG. 6 may be omitted. More particularly, after deposition of the conductor film 16 a made of aluminium or the like according to the low temperature sputtering method having been illustrated in Embodiment 1, the conductor films 16 b, 16 c, each made of aluminium or the like, may be deposited in order from lower layer by the heat sputtering method illustrated in the foregoing Embodiment 1. Additionally, the steps 105, 106 in FIG. 6 may be omitted in some case. More particularly, the conductor film 16 a made of aluminium or the like is deposited at the low temperature sputtering method described in Embodiment 1, followed by annealing (step 104 in FIG. 6) in the same manner as in Embodiment 1 thereby causing grooves or holes to be buried with the conductor film 16 a made of aluminium or the like.

[0058] In the foregoing, applications to the manufacturing method of a semiconductor device having power MIS, which is in the field of utility to which the present invention is directed, have been described, but the invention should not be construed as limiting only to these applications but may be applied, for example, to the manufacturing method of a semiconductor device having IGBT (Insulated Gate Bipolar Transistor) of a trench gate electrode structure. More particularly, the invention is applicable to the technique of forming a base electrode and an emitter electrode of IGBT, each made of aluminium or the like. Alternatively, the invention is also applicable to power IC (integrated circuit) wherein cell arrays, which, respectively, have a plurality of transistor cells each made of a transistor having a trench gate electrode structure and control circuits are mixed in the same substrate.

[0059] The effects of typical embodiments according to the invention are summarized below.

[0060] A first conductor film, which has a structure capable of suppressing or preventing the reaction between aluminium atoms and constituent atoms in a semiconductor substrate upon re-melting or thermal treatment of the conductor film made mainly of aluminium, is deposited on the semiconductor substrate including openings for wiring. Thereafter, the conductor film made mainly of aluminium flows and is charged into the openings for wiring through the thermal treatment for the re-melting after or during the deposition of the conductor film, thus making it possible to suppress or prevent a junction failure from occurring. This eventually leads to improved reliability of the resultant semiconductor device. 

What is claimed is:
 1. A manufacturing method of a semiconductor device, comprising the steps of: (a) forming an opening for wiring over a main surface of a semiconductor substrate in such a way that part of said semiconductor substrate is exposed; (b) depositing a first conductor film over the main surface of said semiconductor substrate including said opening for wiring; (c) depositing an aluminium-based conductor film over said first conductor film including said opening for wiring; and (d) after the step (c), heating said aluminium-based conductor film to cause said conductor film to flow and run into said opening for wiring, wherein said first conductor film has a structure capable of suppressing or preventing, in the step (d), the reaction between aluminium atom in said aluminium-based conductor film and constituent atom in said semiconductor substrate.
 2. The method according to claim 1, further comprising, after the step (b) but prior to the step (c), the step of thermally treating said semiconductor substrate, to form a compound layer made of the constituent atom in said first conductor film and the constituent atom in said semiconductor substrate, at a contact portion between said first conductor film and said semiconductor substrate while leaving said first conductor film at a portion thereof in contact with said aluminium-based conductor film.
 3. The method according to claim 1, further comprising the step of depositing a second conductor film between said first conductor film and said aluminium-based conductor film.
 4. The method according to claim 1, wherein said first conductor film is comprised of titanium tungsten.
 5. The method according to claim 1, wherein said first conductor film is comprised of tungsten, tantalum, tungsten nitride, tantalum nitride or titanium tungsten nitride.
 6. The method according to claim 1, wherein said first conductor film is comprised of a tungsten silicide or tungsten nitride silicide film.
 7. The method according to claim 1, wherein a heating temperature in the step (d) is higher than 400° C.
 8. The method according to claim 1, further comprising, after the step (d), the step of carrying out polishing in such a way that said first conductor film and said aluminium-based conductor film are, respectively, left in said opening for wiring.
 9. A manufacturing method of a semiconductor device, comprising the steps of: (a) forming an opening for wiring over a main surface of a semiconductor substrate in such a way that part of said semiconductor substrate is exposed; (b) depositing a first conductor film over the main surface of said semiconductor substrate including said opening for wiring (c) depositing a first aluminium-based conductor film mainly made of aluminium over said first conductor film including said opening for wiring; and (d) further depositing a second aluminium-based conductor film over said first aluminium-based conductor film including said opening for wiring while heating, so that said first and second aluminium-based conductor films are made to flow and run into said opening for wiring, wherein said first conductor film has a structure capable of suppressing or preventing, in the step (d), the reaction between an aluminium atom in said first and second aluminium-based conductor films and a constituent atom in said semiconductor substrate.
 10. The method according to claim 9, further comprising the step of thermally treating said semiconductor substrate after the step (b) but prior to the step (c), so that a compound layer made of a constituent atom in said first conductor film and a constituent atom of said semiconductor substrate is formed at a contact portion between said first conductor film and said semiconductor substrate, in such a state that said first conductor film is left at a portion in contact with said first and second aluminium-based conductor films.
 11. The method according to claim 9, further comprising depositing a second conductor film between said first conductor film and said first aluminium-based conductor film.
 12. The method according to claim 9, wherein a temperature at which said first aluminium-based conductor film is deposited in the step (c) is lower than a temperature at which said second aluminium-based conductor film is deposited in the step (d).
 13. The method according to claim 9, wherein in the step (d), said second aluminium-based conductor film is deposited at a first rate and further deposited at a second rate higher than said first rate.
 14. The method according to claim 9, wherein said first conductor film is comprised of titanium tungsten.
 15. The method according to claim 9, wherein said first conductor film is comprised of tungsten, tantalum, tungsten nitride, tantalum nitride or titanium tungsten nitride.
 16. The method according to claim 9, wherein said first conductor film is comprised of a tungsten silicide or tungsten nitride silicide film.
 17. The method according to claim 9, wherein a heating temperature in the step (d) is higher than 400° C.
 18. The method according to claim 9, further comprising, after the step (d), the step of carrying out polishing in such a way that said first conductor film and said first and second aluminium-based conductor films are, respectively, left in said opening for wiring.
 19. A manufacturing method of a semiconductor device, comprising the steps of: (a) forming an opening for wiring over a main surface of a semiconductor substrate in such a way that part of said semiconductor substrate is exposed; (b) depositing a first conductor film over the main surface of said semiconductor substrate including said opening for wiring (c) depositing a first aluminium-based conductor film over said first conductor film including said opening for wiring; (d) heating said first aluminium-based conductor film after the step (c) so that said first aluminium-based conductor film is caused to flow and run into said opening for wiring; and (e) depositing, after the step (d), a second aluminium-based conductor film over said first aluminium-based conductor film including said opening for wiring while heating, to cause the first and second aluminium-based conductor films to flow and run into said opening for wiring, wherein said first conductor film has a structure capable of suppressing or preventing, in the steps (d) and (e), the reaction between an aluminium atom and a constituent atom in said semiconductor substrate.
 20. The method according to claim 19, further comprising the step of thermally treating said semiconductor substrate after the step (b) but prior to the step (c), so that a compound layer made of a constituent atom in said first conductor film and a constituent atom of said semiconductor substrate is formed at a contact portion between said first conductor film and said semiconductor substrate, in such a state that said first conductor film is left at a portion in contact with said first and second aluminium-based conductor films.
 21. The method according to claim 19, further comprising the step of depositing a second conductor film between said first conductor film and said first aluminium-based conductor film.
 22. The method according to claim 19, wherein a temperature at which said first aluminium-based conductor film is deposited in the step (c) is lower than a temperature at which said second aluminium-based conductor film is deposited in the step (d).
 23. The method according to claim 19, wherein in the step (d), said second aluminium-based conductor film is deposited at a first rate and further deposited at a second rate higher than said first rate.
 24. The method according to claim 19, wherein said first conductor film is comprised of titanium tungsten.
 25. The method according to claim 19, wherein said first conductor film is comprised of tungsten, tantalum, tungsten nitride, tantalum nitride or titanium tungsten nitride.
 26. The method according to claim 19, wherein said first conductor film is comprised of a tungsten silicide or tungsten nitride silicide film.
 27. The method according to claim 19, wherein a heating temperature in the step (d) is higher than 400° C.
 28. The method according to claim 19, wherein a heating temperature in the step (e) is higher than 400° C.
 29. The method according to claim 19, further comprising, after the step (e), the step of carrying out polishing in such a way that said first conductor film and said first and second aluminium-based conductor films are, respectively, left in said opening for wiring.
 30. A manufacturing method of a semiconductor device having a power transistor, comprising the steps of: (a) forming a first semiconductor region of a first conductivity type in a semiconductor substrate; (b) forming a second semiconductor region of a second conductivity type opposite to said first conductivity type as an upper layer relative to said first semiconductor region of said semiconductor substrate; (c) forming a gate insulating film on said semiconductor substrate; (d) forming a gate electrode on said gate insulating film; (e) forming a first insulating film on said gate electrode; (f) forming a second insulating film at side surfaces of said gate electrode; (g) etching part of said semiconductor substrate exposed from said first and second insulating films thereby forming a groove passing through said second semiconductor region to reach said first semiconductor region; (h) forming a third semiconductor region of said first conductivity type at a bottom of said groove; (i) depositing a first conductor film over the main surface of said semiconductor substrate including an inside of said groove; (j) depositing an aluminium-based conductor film on said first conductor film including the inside of said groove; and (k) after the step (j), heating said aluminium-based conductor film to cause said aluminium-based conductor film to flow and run into said groove, wherein said first conductor film has a structure capable of suppressing or preventing, in the step (k), the reaction between aluminium atom in said aluminium-based conductor film and constituent atom in said semiconductor substrate.
 31. A manufacturing method of a semiconductor device having a power transistor, comprising the steps of: (a) forming a first semiconductor region of a first conductivity type in a semiconductor substrate; (b) forming a second semiconductor region of a second conductivity type opposite to said first conductivity type as an upper layer relative to said first semiconductor region of said semiconductor substrate; (c) forming a gate insulating film over said semiconductor substrate; (d) forming a gate electrode on said gate insulating film; (e) forming a first insulating film on said gate electrode; (f) forming a second insulating film at side surfaces of said gate electrode; (g) etching part of said semiconductor substrate exposed from said first and second insulating films thereby forming a groove passing through said second semiconductor region to reach said first semiconductor region; (h) forming a third semiconductor region of said first conductivity type at a bottom of said groove; (i) depositing a first conductor film over the main surface of said semiconductor substrate including an inside of said groove; (j) depositing a first aluminium-based conductor film over said first conductor film including the inside of said groove; and (k) depositing a second aluminium-based conductor film over said first aluminium-based conductor film including the inside of said groove while heating, thereby causing said first and second aluminium-based conductor films to run into said groove, wherein said first conductor film has a structure capable of suppressing or preventing, in the step (k), the reaction between aluminium atom in said first and second aluminium-based conductor films and a constituent atom in said semiconductor substrate.
 32. A manufacturing method of a semiconductor device having a power transistor, comprising the steps of: (a) forming a first semiconductor region of a first conductivity type in a semiconductor substrate; (b) forming a second semiconductor region of a second conductivity type opposite to said first conductivity type as an upper layer relative to said first semiconductor region of said semiconductor substrate; (c) forming a gate insulating film over said semiconductor substrate; (d) forming a gate electrode over said gate insulating film; (e) forming a first insulating film over said gate electrode; (f) forming a second insulating film at side surfaces of said gate electrode; (g) etching part of said semiconductor substrate exposed from said first and second insulating films thereby forming a groove passing through said second semiconductor region to reach said first semiconductor region; (h) forming a third semiconductor region of said first conductivity type at a bottom of said groove; (i) depositing a first conductor film over the main surface of said semiconductor substrate including an inside of said groove; (j) depositing a first aluminium-based conductor film over said first conductor film including the inside of said groove; (k) heating, after the step (j), said first aluminium-based conductor film, thereby causing said first aluminium-based conductor film to flow and run into said groove; and (l) depositing, after the step (k), a second aluminium-based conductor film over said first aluminium-based conductor film including the inside of said groove while heating, thereby causing said first and second aluminium-based conductor films to run into said groove, wherein said first conductor film has a structure capable of suppressing or preventing, in the steps (k) and (l), the reaction between aluminium atom and constituent atom in said semiconductor substrate.
 33. A manufacturing method of a semiconductor device having a power transistor, comprising the steps of: (a) forming, in a semiconductor substrate, a first semiconductor region of a first conductivity type where a channel region of said power transistor is to be formed; (b) forming a second semiconductor region of a second conductivity type, which is opposite to said first conductivity type and serves as a source region of said power transistor, as an upper layer relative to said first semiconductor region of said semiconductor substrate; (c) forming, in said semiconductor substrate, a first groove reaching a position deeper than said first semiconductor region; (d) forming a gate insulating film over a main surface of said semiconductor substrate including an inside of said first groove; (e) forming a gate electrode over said gate insulating film including the inside of said first groove; (f) forming a first insulating film over said gate electrode; (g) forming a second insulating film at side surfaces of said gate electrode; (h) etching part of said semiconductor substrate exposed from said first and second insulating films thereby forming a second groove passing through said second semiconductor region to reach said first semiconductor region; (i) forming a third semiconductor region of said first conductivity type at a bottom of said second groove; (j) depositing a first conductor film over the main surface of said semiconductor substrate including an inside of said second groove; (k) depositing a first aluminium-based conductor film over said first conductor film including the inside of said second groove; (l) heating, after the step (k), said first aluminium-based conductor film, thereby causing said aluminium-based conductor film to flow and run into said second groove; and (m) patterning said conductor film and said aluminium-based conductor film to form a gate electrode and a source electrode of said power transistor, wherein said first conductor film has a structure capable of suppressing or preventing, in the step (l), the reaction between aluminium atom in said aluminium-based conductor film and constituent atom in said semiconductor substrate.
 34. A manufacturing method of a semiconductor device having a power transistor, comprising the steps of: (a) forming, in a semiconductor substrate, a first semiconductor region of a first conductivity type where a channel region of said power transistor is to be formed; (b) forming a second semiconductor region of a second conductivity type, which is opposite to said first conductivity type and serves as a source region of said power transistor, as an upper layer relative to said first semiconductor region of said semiconductor substrate; (c) forming, in said semiconductor substrate, a first groove reaching a position deeper than said first semiconductor region; (d) forming a gate insulating film over a main surface of said semiconductor substrate including an inside of said first groove; (e) forming a gate electrode over said gate insulating film including the inside of said first groove; (f) forming a first insulating film over said gate electrode; (g) forming a second insulating film at side surfaces of said gate electrode; (h) etching part of said semiconductor substrate exposed from said first and second insulating films thereby forming a second groove passing through said second semiconductor region to reach said first semiconductor region; (i) forming a third semiconductor region of said first conductivity type at a bottom of said second groove; (j) depositing a first conductor film over the main surface of said semiconductor substrate including an inside of said second groove; (k) depositing a first aluminium-based conductor film over said first conductor film including the inside of said second groove; (l) depositing a second aluminium-based conductor film over said first aluminium-based conductor film including the inside of said second groove while heating thereby causing said first and second aluminium-based conductor films to run into said second groove; and (m) patterning said first conductor film and said first and second aluminium-based conductor films to form a gate electrode and a source electrode of said power transistor, wherein said first conductor film has a structure capable of suppressing or preventing, in the step (l), the reaction between aluminium atom in said first and second aluminium-based conductor films and constituent atom in said semiconductor substrate.
 35. A manufacturing method of a semiconductor device having a power transistor, comprising the steps of: (a) forming, in a semiconductor substrate, a first semiconductor region of a first conductivity type where a channel region of said power transistor is to be formed; (b) forming a second semiconductor region of a second conductivity type, which is opposite to said first conductivity type and serves as a source region of said power transistor, as an upper layer relative to said first semiconductor region of said semiconductor substrate; (c) forming, in said semiconductor substrate, a first groove reaching a position deeper than said first semiconductor region; (d) forming a gate insulating film over a main surface of said semiconductor substrate including an inside of said first groove; (e) forming a gate electrode over said gate insulating film including the inside of said first groove; (f) forming a first insulating film over said gate electrode; (g) forming a second insulating film at side surfaces of said gate electrode; (h) etching part of said semiconductor substrate exposed from said first and second insulating films thereby forming a second groove passing through said second semiconductor region to reach said first semiconductor region; (i) forming a third semiconductor region of said first conductivity type at a bottom of said second groove; (j) depositing a first conductor film over the main surface of said semiconductor substrate including an inside of said second groove; (k) depositing a first aluminium-based conductor film over said first conductor film including the inside of said second groove; (l) heating, after the step (k), said first aluminium-based conductor film thereby causing said first aluminium-based conductor film to run into the inside of said second groove; (m) depositing, after the step (l), a second aluminium-based conductor film over said first aluminium-based conductor film including the inside of said second groove while heating thereby causing said first and second aluminium-based conductor films to flow and run into said second groove; and (n) patterning said first conductor film and said first and second aluminium-based conductor films to form a gate electrode and a source electrode of said power transistor, wherein said first conductor film has a structure capable of suppressing or preventing, in the steps (l) and (m), the reaction between aluminium atom and constituent atom in said semiconductor substrate. 